The present invention relates to information handling systems, and more particularly to direct memory access of memory in personal computer systems.
Generally in computer systems and especially in personal computer systems, data are transferred between various elements such as a central processing unit (CPU), memory devices and direct memory access (DMA) control circuitry as well as expansion devices such as input/output (I/O) adapters, bus controllers (i.e., elements which can control the computer system), bus slaves (i.e., elements which are controlled by bus controllers). The expansion devices are often interconnected via a system I/O bus. The DMA control circuitry is used to transfer information to and from memory devices without using the CPU; generally, once the CPU has provided the DMA control circuitry with control information such as the base location from where information is to be moved, the address of where the data information should go, and the size of the data information to be moved, the DMA control circuitry controls the transfer of the data information.
Often it is desirable to temporarily hold data which is being transferred from one location to another. It is known to temporarily hold data by using, e.g., write back buffers, register arrays, small static memory buffers and first in, first out (FIFO) buffers. With a FIFO buffer, data are provided to the input terminals of the FIFO, temporarily held by the FIFO and provided to the output terminals of the FIFO. Characteristics which are desirable in a FIFO buffer include speed, expandability and self-containment. A FIFO buffer should be fast enough to allow back to back read and write accesses in any order without additional wait states. A FIFO buffer should be expandable to support wider buses, referred to as buffer width, as well as expandable to allow additional storage, referred to as buffer depth; it is also desirable to allow expansion without the necessity of changing the system requirements of the FIFO, i.e., without requiring changing the control information which is provided to the FIFO.
It is known to configure FIFO buffers in a plurality of arrangements. In a first arrangement, called a mux-in/mux-out arrangement, data are provided to a layer of multiplexers. The data are multiplexed until ultimately, at the output stage, a single multiplexer provides the output signal. The FIFO is widened by providing additional input signals to the existing arrangement of multiplexers. This arrangement allows immediate access to any data cell at any time; however, the output multiplexer increases substantially as additional data cells are added. Thus increasing cell count and data propagation delay.
In a second arrangement, called a shift register arrangement, data are provided to an array of shift registers and shifted down to an output stage. An additional row of shift registers is added to the arrangement to widen the FIFO. This arrangement allows adding additional data cells without adding additional output multiplexer cells or data propagation delay. However, data information which is presented to the input terminals of the FIFO cannot be immediately accessed due to the shifting process.